The present application relates to semiconductor devices, and more particularly, to the formation of uniform source/drain junctions in fin field effect transistors (FinFETs) with sigma-shaped source/drain regions.
Applying stress to the channel of a field effect transistor (FET) is desirable to increase the speed of the device. One way of generating stress in the channel of an FET is to embed a stress-generating material within source and drain (i.e., source/drain) regions of the FET. The embedded structures can be formed by etching portions of the source/drain regions to form cavities, and refilling the cavities with a doped stress-generating material by epitaxy.
Embedding “sigma-shaped” structures in source/drain regions of a FinFET has been approved to be an effective approach for channel strain enhancement. FIG. 1 depicts a prior art structure 100 including a semiconductor fin 110 located on a substrate (not shown), gate structures 120 formed over the semiconductor fin 110, and a sigma-shaped source/drain structure 130 embedded in a sigma cavity 132 between the gate structures 120. The sigma-shaped source/drain structure 130 allows for close proximities towards the transistor channel region 140 and therefore maximizing stress inside the transistor channel region 140. However, for FinFETs, the subsequent drive-in anneal performed on such sigma-shaped source/drain structure 130 results in a non-uniform junction profile 150, along the fin height direction, yielding in gate length variation within each semiconductor fin. Therefore, an embedded source/drain structure and process that provide a uniform source/drain junction profile are needed.
Moreover, to create more stress on the channel, a greater volume of stress-generating material is desired, therefore a sigma cavity with a greater sigma tip depth (d) is needed. However, for FinFETs with narrow gates, forming a sigma cavity with a deeper sigma tip is challenging because of the limitation on the extent of the lateral etch that is used to form the sigma cavity. The excessive lateral etch may cause exposure of the gate material. The sigma tip depth (d) is typically about 10 nm, which is far less than the active fin height (D) (about 35 nm). Therefore, an embedded source/drain structure and process which can maximize volume of the stress-generating material, while providing a uniform source/drain junction profile for narrow gate FinFETs, are needed.